1. Field of the Invention
The present invention relates to a technique of connecting and encapsulating a semiconductor chip to a mounting-member by a flip chip method and, more particularly, to a semiconductor device in which the structure and connected state near the electrodes of a semiconductor chip and a mounting-member are improved, and a method of fabricating the same.
2. Description of the Related Art
Steps of electrically connecting a semiconductor chip onto a mounting-member such as a package, and adhering and encapsulating the semiconductor chip and a mounting-member by a general flip chip wireless bonding method will be briefly explained below.
For example, as shown in FIG. 7, a semiconductor chip 101 and a glass-epoxy-substrate 103 as a mounting-member are opposed to each other. In this state, a gold (Au) stud-bump 102 and a copper (Cu) lead 104 formed on the substrate 103 are aligned. On the lead 104, an Sn—Ag plated-bump 105 which is a thick projection (projected-member) having substantially the same size as the width of the lead 104 is stacked beforehand by electroplating. This plated-bump 105 can also be formed using Sn. The width of the plated-bump 105 is more specifically about 50 μm.
An encapsulating resin 106 such as a thermosetting insulating film is filled between the chip 101 and the substrate 103. In this state, the chip 101 is adhered to the substrate 103 by thermocompression. Consequently, as shown in FIG. 8, the stud-bump 102 and lead 104 are connected via the plated-bump 105. That is, the electrical connection between the stud-bump 102 and lead 104 and the encapsulation of the semiconductor chip 101 and the glass-epoxy-substrate 103 with the encapsulating resin 106 are simultaneously performed.
Recently, in the field of semiconductor device fabrication technology, small lead pitches are increasingly demanded along with advanced micropatterning and an increase in density of devices. That is, it is more and more demanded to decrease lead pitches. However, the width of a normal plated-bump 105 is as large as about 50 μm, and this is the largest obstacle to decreasing pitches. Unfortunately, if the width of the lead 104 is simply decreased, the stacking position of the plated-bump 105 easily deviates when this plated-bump 105 is formed on the lead 104, or the plated-bump 105 easily falls from the lead 104. As a consequence, poor electrical connection may occur between the stud-bump 102, lead 104, and plated-bump 105. This may lead to deterioration of the quality such as the electrical performance and reliability of the semiconductor device. Furthermore, the positional deviation of the plated-bump 105 lowers the fabrication yield of the semiconductor device. This may decrease the production efficiency of the semiconductor device.